A symbolic execution framework for algorithm-level modelling

• Published in: 2009 IEEE International High Level Design Validation and Test Workshop pp. 94 - 99
• Main Authors: Hanna, Z., Melham, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2009
• Subjects: Algorithm design and analysis; Circuits; Clocks; Convergence; Formal verification; Job shop scheduling; Laboratories; Microarchitecture; Object oriented modeling; Specification languages
• ISSN: 1552-6674; 2471-7827
• DOI: 10.1109/HLDVT.2009.5340168

This work aims to address the well-known and acute challenge of functional validation for complex, contemporary microarchitectural circuit designs. We provide a new formal framework for algorithm level modelling - design modelling at a high abstraction level, focused exclusively on function and algorithms. The semantics of our models is based on abstract state machines with synchronous parallel execution, sequential execution, and nondeterminism. To express models we propose an executable, object-oriented architecture specification language with rich data types and a well-defined formal semantics, based initially on Microsoft's AsmL. We describe an experimental framework for direct symbolic execution of models in this language, intended as a basis for both property and refinement verification, as well as design exploration. We explain and illustrate our approach through a case study, the modelling a simple muop scheduler and its refinement towards a design model for circuit implementation. We aim to show the utility of our language and symbolic execution framework for exploring microarchitectural algorithm and to validate designs using dynamic or formal techniques, yielding more productive convergence to high quality implementations.