A 1.08-Gb/s burst-mode clock and data recovery circuit using the jitter reduction technique

A 1.08-Gb/s CMOS half-rate burst-mode clock and data recovery (BMCDR) circuit with a novel jitter reduction technique is presented. There are several discrete delay time values in the programmable delay circuit (PDC) of the edge detector can be selected by five addressing inputs to create a "dy...

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Bibliographic Details
Published in2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1899 - 1902
Main Authors Kae-Dyi You, Herming Chiueh
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
Subjects
Circuit noise
Clocks
CMOS technology
Delay effects
Detectors
Fluctuations
Jitter
Passive optical networks
Phase locked loops
Voltage-controlled oscillators
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Summary:A 1.08-Gb/s CMOS half-rate burst-mode clock and data recovery (BMCDR) circuit with a novel jitter reduction technique is presented. There are several discrete delay time values in the programmable delay circuit (PDC) of the edge detector can be selected by five addressing inputs to create a "dynamic average" delay time that equals to half-of-data period (T bit /2) to ensure minimum jitter accumulation. A prototype chip was designed with TSMC 0.18-mum CMOS 1P6M technology. The occupied die area of the CDR is 0.99 times 0.97 mm 2 , and the power consumption is 36 mW under a 1.8-V supply voltage.
ISBN:1424438276
9781424438273
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2009.5118151