Probabilistic error propagation in logic circuits using the Boolean difference calculus

• Published in: 2008 IEEE International Conference on Computer Design pp. 7 - 13
• Main Authors: Mohyuddin, N., Pakbaznia, E., Pedram, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2008
• Subjects: Boolean functions; Calculus; Circuit faults; Electronic mail; Error analysis; Error probability; Logic circuits; Switches; Switching circuits; Tensile stress

A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Bool...