Probabilistic error propagation in logic circuits using the Boolean difference calculus

A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Bool...

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Bibliographic Details
Published in2008 IEEE International Conference on Computer Design pp. 7 - 13
Main Authors Mohyuddin, N., Pakbaznia, E., Pedram, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2008
Subjects
Boolean functions
Calculus
Circuit faults
Electronic mail
Error analysis
Error probability
Logic circuits
Switches
Switching circuits
Tensile stress
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Summary:A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Boolean difference calculus and can be applied to the problem of calculating the error probability at the primary outputs of a multi-level Boolean circuit with a time complexity which is linear in the number of gates in the circuit. This is done by starting from the primary inputs and moving toward the primary outputs by using a post-order traversal. Experimental results demonstrate the accuracy and efficiency of the proposed approach compared to the other known methods for error calculation in VLSI circuits.
ISBN:9781424426577
142442657X
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2008.4751833