Addressing link-level design tradeoffs for integrated photonic interconnects

Integrated photonic interconnects have emerged recently as a potential solution for relieving on-chip and chip-to-chip bandwidth bottlenecks for next-generation many-core processors. To help bridge the gap between device and circuit/system designers, and aid in understanding of inherent photonic lin...

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Bibliographic Details
Published in2011 IEEE Custom Integrated Circuits Conference (CICC) pp. 1 - 8
Main Authors Georgas, M., Leu, J., Moss, B., Chen Sun, Stojanovic, V.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2011
Subjects
Clocks
Modulation
Optical buffering
Optical receivers
Photonics
Sensitivity
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Summary:Integrated photonic interconnects have emerged recently as a potential solution for relieving on-chip and chip-to-chip bandwidth bottlenecks for next-generation many-core processors. To help bridge the gap between device and circuit/system designers, and aid in understanding of inherent photonic link tradeoffs, we present a set of link component models for performing interconnect design-space exploration connected to the underlying device and circuit technology. To compensate for process and thermal-induced ring resonator mismatches, we take advantage of device and circuit characteristics to propose an efficient ring tuning solution. Finally, we perform optimization of a wavelength-division-multiplexed link, demonstrating the link-level interactions between components in achieving the optimal degree of parallelism and energy-efficiency.
ISBN:9781457702228
1457702223
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2011.6055363