Using cutwidth to improve symbolic simulation and Boolean satisfiability

In this paper, we propose cutwidth based heuristics to improve the efficiency of symbolic simulation and SAT algorithms. These algorithms are the underlying engines of many formal verification techniques. We present a new approach for computing variable orderings that reduce CNF/circuit cutwidth. We...

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Bibliographic Details
Published inSixth IEEE International High-Level Design Validation and Test Workshop pp. 165 - 170
Main Authors Dong Wang, Clarke, E., Yunshan Zhu, Kukula, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Automatic test pattern generation
Binary decision diagrams
Boolean functions
Circuit simulation
Computational modeling
Data structures
Engines
Formal verification
Length measurement
Runtime
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Summary:In this paper, we propose cutwidth based heuristics to improve the efficiency of symbolic simulation and SAT algorithms. These algorithms are the underlying engines of many formal verification techniques. We present a new approach for computing variable orderings that reduce CNF/circuit cutwidth. We show that the circuit cutwidth and the peak number of live BDDs during symbolic simulation are equal. Thus using an ordering that reduces the cutwidth in scheduling the gates during symbolic simulation can significantly improve both the runtime and memory requirements. It has been shown that the time complexity of SAT problems can be bounded exponentially by the formula cutwidth and many practical circuits has cutwidth logarithmic of the size of the formulas. We have developed cutwidth based heuristics which in practice can speed up existing SAT algorithms, especially for SAT instances with small cutwidth. We demonstrate the power of our approach on a number of standard benchmarks.
ISBN:0769514111
9780769514116
DOI:10.1109/HLDVT.2001.972824