Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

The ability of a compiler to exploit loop-level parallelism in a reconfigurable array is significantly affected by the amount of flexibility in the interconnect architecture. A less flexible interconnect will make it more difficult for the compiler to find efficient loop-level pipelined schedules, l...

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Bibliographic Details
Published inProceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921) pp. 33 - 40
Main Authors Wilton, S.J.E., Kafafi, N., Bingfeng Mei, Vernalde, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2004
Subjects
Clocks
Computer architecture
Fabrics
Field programmable gate arrays
Network topology
Power dissipation
Power supplies
Power system interconnection
Routing
Throughput
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Summary:The ability of a compiler to exploit loop-level parallelism in a reconfigurable array is significantly affected by the amount of flexibility in the interconnect architecture. A less flexible interconnect will make it more difficult for the compiler to find efficient loop-level pipelined schedules, leading to reduced instruction throughput, and larger configuration bit storage area. In this paper, we determine the optimum flexibility and topology for a point-to-point interconnect architecture in a reconfigurable system. We present four topologies, and show that their performance per unit area is significantly better than that that would be obtained if a fully-connected network had been used.
ISBN:0780386515
9780780386518
DOI:10.1109/FPT.2004.1393248