Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath

• Published in: 2009 International Conference on Reconfigurable Computing and FPGAs pp. 261 - 266
• Main Authors: Grossschadl, J., Savas, E., Yumbul, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2009
• Subjects: Arithmetic; Bit-serial multiplier architecture; Clocks; Cryptography; Field programmable gate arrays; Hardware; Montgomery modular multiplication; Scalability; Security; Silicon; Software algorithms; Software standards
• ISBN: 9781424452934; 1424452937
• ISSN: 2325-6532; 2640-0472
• DOI: 10.1109/ReConFig.2009.83

Within the context of cryptographic hardware, the term scalability refers to the ability to process operands of any size, regardless of the precision of the underlying datapath or registers. In this paper we present a simple yet effective technique for increasing the scalability of a fixed-precision Montgomery multiplier. Our idea is to extend the datapath of a Montgomery multiplier in such a way that it can also perform an ordinary multiplication of two n-bit operands (without modular reduction), yielding a 2n-bit result. This conventional (n × n ¿ 2n)-bit multiplication is then used as a "sub-routine" to realize arbitrary-precision Montgomery multiplication according to standard software algorithms such as Coarsely Integrated Operand Scanning (CIOS). We show that performing a 2n-bit modular multiplication on an n-bit multiplier can be done in 5n clock cycles, whereby we assume that the n-bit modular multiplication takes n cycles. Extending a Montgomery multiplier for this extra functionality requires just some minor modifications of the datapath and entails a slight increase in silicon area.