Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementat...

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Bibliographic Details
Published in2009 39th International Symposium on Multiple-Valued Logic pp. 233 - 238
Main Authors Melis, W.J.C., Chizuwa, S., Kameyama, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
Subjects
Animals
Bayesian methods
Brain modeling
Computer architecture
Feature extraction
Hardware
Home appliances
Humans
Logic
probabilistic systems
soft computing
user support systems
Very large scale integration
VLSI
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Summary:A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementation of one such user support system, namely an intention estimation information appliance system, on a Bayesian network as well as hierarchical temporal memory. The latter is a new and quite promising soft computing platform modelling the human brain, though currently only available as a software model. A second part of the paper therefore focuses on a possible VLSI architecture for hierarchical temporal memory. Since it models the human brain, communication as well as memory are of high importance for this VLSI architecture.
ISBN:1424438411
9781424438419
ISSN:0195-623X
2378-2226
DOI:10.1109/ISMVL.2009.11