VGTA: variation-aware gate timing analysis

• Published in: 2005 International Conference on Computer Design pp. 351 - 356
• Main Authors: Abbaspour, S., Fatemi, H., Pedram, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Capacitance; Delay; Digital integrated circuits; Integrated circuit interconnections; Integrated circuit technology; Libraries; Runtime; Timing; Very large scale integration; Wire
• ISBN: 0769524516; 9780769524511
• ISSN: 1063-6404; 2576-6996
• DOI: 10.1109/ICCD.2005.115

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to gate and wire variability. Therefore, statistical timing analysis is inevitable. Most timing tools divide the analysis into two parts: 1) interconnect (wire) timing analysis and 2) gate timing analysis. Variational interconnect delay calculation for block-based /spl sigma/TA has been recently studied. However, variational gate delay calculation has remained unexplored. In this paper, we propose a new framework to handle the variation-aware gate timing analysis in block-based /spl sigma/TA. First, we present an approach to approximate variational RC-/spl pi/ load by using a canonical first-order model. Next, an efficient variation-aware effective capacitance calculation based on statistical input transition, statistical gate timing library, and statistical RC-/spl pi/ load is presented. In this step, we use a single-iteration C/sub eff/ calculation which is efficient and reasonably accurate. Finally we calculate the statistical gate delay and output slew based on the aforementioned model. Experimental results show an average error of 7% for gate delay and output slew with respect to the HSPICE Monte Carlo simulation while the runtime is about 145 times faster.