Principles of timing anomalies in superscalar processors

• Published in: Fifth International Conference on Quality Software (QSIC'05) pp. 295 - 303
• Main Authors: Wenzel, I., Kirner, R., Puschner, P., Rieder, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Control systems; Distributed control; Hardware; Parallel processing; Performance analysis; Pipelines; Real time systems; Resource management; Solids; Timing
• ISBN: 0769524729; 9780769524726
• ISSN: 1550-6002; 2332-662X
• DOI: 10.1109/QSIC.2005.49

The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies. In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-orderfunctional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor. This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.