Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

• Published in: 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines pp. 17 - 24
• Main Authors: Jongsok Choi, Nam, K., Canis, A., Anderson, J., Brown, S., Czajkowski, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2012
• Subjects: Benchmark testing; Field programmable gate arrays; Hardware; Memory architecture; Memory management; Random access memory
• ISBN: 9781467316057; 1467316059
• DOI: 10.1109/FCCM.2012.13

We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator context, we examine the impact of the cache design and its interface. Specifically, we look at how the number of cache ports affects performance when multiple hardware accelerators operate (and access memory) in parallel, and evaluate two different hardware implementations of multi-ported caches using: 1) multi-pumping, and 2) a recently-published approach based on the concept of a live-value table. Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speed up swings from 0.73× to 6.14×, on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines). Considering both performance and area, the best architecture is found to be a 4-port multi-pump direct-mapped cache with a 16KB cache size and a 128B line size.