Building verification condition generators by compositional extensions

• Published in: Third IEEE International Conference on Software Engineering and Formal Methods (SEFM'05) pp. 220 - 229
• Main Authors: Prasetya, I.S.W.B., Fakultas, A.A., Vos, T.E.J., van Leeuwen, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Algebra; Delay; Java; Logic functions; Logic programming; modular verification; Software engineering; verification technique; verification tool
• ISBN: 0769524354; 9780769524351
• ISSN: 1551-0255; 2160-7656
• DOI: 10.1109/SEFM.2005.11

This paper describes a technique that combines algebraic datatypes and monads to build derivative verification condition generators (VCGs) by extending a base VCG. Extensions are compositional and can be stacked while the base VCG is left unchanged. The technique can be used to build a set of weaker VCGs to do light weight verification. Moreover, it enables us to add an ability to generate validation traces. The paper explains the technique through an example that extends a simple language L/sub 0/ with new constructs to handle exceptions. To deal with exceptions, not only the logic of L/sub 0/ has to be extended with new rules, its structure also needs to be changed. We show that using our technique the extension can be implemented in a simple and compositional way, without any change to the underlying logic.