Timing Fault Detection in FPGA-Based Circuits

The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial ene...

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Bibliographic Details
Published in2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines pp. 96 - 99
Main Authors Stott, Edward, Levine, Joshua M., Cheung, Peter Y. K., Kapre, Nachiket
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2014
Subjects
Clocks
Electrical fault detection
Fault detection
Field programmable gate arrays
Registers
Timing
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Summary:The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial energy and performance improvements. However, doing this carelessly would cause unacceptable impacts to reliability, lifespan and yield - issues which are growing more severe with continuing process scaling. Fortunately, the flexibility of FPGA architecture allows us to monitor and control reliability problems with a variety of runtime instrumentation and adaptation techniques. In this paper we develop a system for detecting timing faults in arbitrary FPGA circuits based on Razor-like shadow register insertion. Through a combination of calibration, timing constraint and adaptation of the CAD flow, we deliver low-overhead, trustworthy fault detection for FPGA-based circuits.
DOI:10.1109/FCCM.2014.32