Dual-Processor Design of Energy Efficient Fault-Tolerant System

A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the primary copy. If there is no fault, the secondary processor terminates its execution. Otherwise, should the fault occur, the...

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Bibliographic Details
Published inIEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) pp. 239 - 244
Main Authors Shaoxiong Hua, Pari, P.R., Gang Qu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2006
Subjects
Circuit faults
Dynamic scheduling
Energy consumption
Energy efficiency
Fault tolerance
Fault tolerant systems
Heuristic algorithms
Real time systems
Redundancy
Voltage
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Summary:A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the primary copy. If there is no fault, the secondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual-processor system. Specifically, we first derive an optimal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system's energy consumption at run time by taking advantage of the actual execution time which is less than the WCET. Simulation on real-life benchmark applications shows that our technique can save up to 80% energy while still providing fault tolerance
ISBN:0769526829
9780769526829
ISSN:1063-6862
DOI:10.1109/ASAP.2006.27