Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration

This paper explores the utilization of run-time partial dynamic reconfiguration in the LEON3 open-source soft core processor, which is a highly configurable SPARC (scalable processor architecture) V8 instruction set processor. The work explores the possibilities of sharing different arithmetic funct...

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Bibliographic Details
Published in2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools pp. 592 - 598
Main Authors Zaidi, I., Nabina, A., Canagarajah, C.N., Nunez-Yanez, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
Clocks
Control systems
Costs
Delay
Energy consumption
Fabrics
Field programmable gate arrays
Hardware
Internal Configuration access Port
Leon3
Open source software
Partial Dynamic Reconfiguration
Pipelines
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Summary:This paper explores the utilization of run-time partial dynamic reconfiguration in the LEON3 open-source soft core processor, which is a highly configurable SPARC (scalable processor architecture) V8 instruction set processor. The work explores the possibilities of sharing different arithmetic functions tightly coupled to the integer pipeline and mapped to the same silicon area, saving power consumption and area utilisation. The same strategy can be used to extend the instruction set architecture of the processor with new instructions that are optimized for DSP applications. The logic necessary to support these instructions could then be swapped as demanded by the application.
ISBN:9780769532776
0769532772
DOI:10.1109/DSD.2008.92