Thread Count Prediction Model: Dynamically Adjusting Threads for Heterogeneous Many-Core Systems

• Published in: 2015 IEEE 21st International Conference on Parallel and Distributed Systems (ICPADS) pp. 456 - 464
• Main Authors: Ju, Tao, Wu, Weiguo, Chen, Heng, Zhu, Zhengdong, Dong, Xiaoshe
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.12.2015
• Subjects: Benchmark testing; Computation; Computing performance; Counting; Dynamical systems; Dynamics; Energy consumption; Energy efficiency; Heterogeneous computing; Heterogeneous many-core system; Instruction sets; Mathematical models; Message systems; Microwave integrated circuits; Multicore processing; Optimization; Optimum thread count; Performance enhancement; Prediction model; Predictive models
• ISSN: 2690-5965; 1521-9097
• DOI: 10.1109/ICPADS.2015.64

Determining an appropriate thread count for a multithread application running on a heterogeneous many-core system is crucial for improving computing performance and reducing energy consumption. This paper investigates the interrelation between thread count and computing performance of applications, and designs a prediction model of the optimum thread count on the basis of Amdahl's law combined with regression analysis theory to improve computing performance and reduce energy consumption. The prediction model can estimate the optimum tread count relying on the program running behaviors and the architecture characteristics of heterogeneous many-core system. Using the estimated optimum thread count, the number of the active hardware threads and processing cores on the many-core processor is dynamically adjusted in the process of thread mapping to improve the energy efficiency of entire heterogeneous many-core system. The experimental results show that, using this paper proposed thread count prediction model, on an average, the computing performance is improved by 48.6%, energy consumption is reduced by 59%, and additional overhead introduced is 2.03% compared with that of the traditional thread mapping for the PARSEC benchmark programs run on an Intel MIC heterogeneous many-core system.