On using Schmitt trigger for digital logic

This paper looks at a classical CMOS NOR-2 gate as well as Schmitt trigger (ST) versions, when the transistors are sized conventionally and unconventionally. ST gates exhibit positive feedback leading to better static noise margins (SNMs), hence less sensitive to noises (i.e., more reliable). The ST...

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Bibliographic Details
Published in2015 International Semiconductor Conference (CAS) pp. 197 - 200
Main Authors Beiu, Valeriu, Tache, Mihai
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.10.2015
Subjects
CMOS
CMOS integrated circuits
Conferences
Delays
Digital
Gates
Integrated circuit reliability
Logic
Logic gates
Noise
NOR-2
Optimized production technology
power
reliability
Schmitt trigger
Schmitt triggers
Semiconductors
sizing
static noise margin (SNM)
Transistors
Voltage
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Summary:This paper looks at a classical CMOS NOR-2 gate as well as Schmitt trigger (ST) versions, when the transistors are sized conventionally and unconventionally. ST gates exhibit positive feedback leading to better static noise margins (SNMs), hence less sensitive to noises (i.e., more reliable). The ST concept has lately been used for SRAM cells, with a few papers targeting digital logic. Here we explore the whole voltage and performance range, characterizing SNM, power, delay, and power-delay-product of ST NOR-2 gates, with the aim of getting a better understanding of their advantages for digital logic.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
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SourceType-Conference Papers & Proceedings-2
ISBN:9781479988624
1479988626
ISSN:1545-827X
2377-0678
DOI:10.1109/SMICND.2015.7355206