Design and implementation of truncated multipliers for precision improvement

Truncated multipliers offers significant improvements in area, delay, and power. The proposed method finally reduces the number of full adders and half adders during the tree reduction. While using this proposed method experimentally, area can be saved. The output is in the form of LSB and MSB. Fina...

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Bibliographic Details
Published in2013 International Conference on Computer Communication and Informatics pp. 1 - 6
Main Authors Devarani, R., Manikandababu, C. S.
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.01.2013
Subjects
Adders
Circuits
Computer architecture
Computer arithmetic
Computers
Conferences
Delay
Deletion
Error compensation
faithful rounding
Finite wordlength effects
fixed-width multiplier
Informatics
Multipliers
Reduction
tree reduction
truncated multiplier
Truncation errors
Very large scale integration
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Summary:Truncated multipliers offers significant improvements in area, delay, and power. The proposed method finally reduces the number of full adders and half adders during the tree reduction. While using this proposed method experimentally, area can be saved. The output is in the form of LSB and MSB. Finally the LSB part is compressed by using operations such as deletion, reduction, truncation, rounding and final addition. In previous related papers, to reduce the truncation error by adding error compensation circuits. In this project truncation error is not more than 1 ulp (unit of least position). So there is no need of error compensation circuits, and the final output will be précised.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
ObjectType-Feature-3
content type line 23
SourceType-Conference Papers & Proceedings-2
ISBN:1467329061
9781467329064
DOI:10.1109/ICCCI.2013.6466244