Device specific characterization of yield limiting pattern geometries by combining layout profiling with high sensitivity wafer inspection

This paper reports on a new approach to capture the impact of marginal pattern geometries on occurrence of systematic yield-limiting defects. Layout profiling and Hot-Spot checking techniques were used to mark new incoming device layout for regions that approached the known marginal pattern geometri...

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Bibliographic Details
Published in2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) pp. 146 - 149
Main Authors Le Denmat, Jean-Christophe, Tetar, Laurent, Fanton, Pierre, Yesilada, Emek, Goirand, Pierre-Jerome, Narasimhan, Narayani, Parisi, Paolo, Ramachandran, Vijay, Kekare, Sagar A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2015
Subjects
Advanced Patterning
Design-for-Manufacturing
Geometry
Inspection
Layout
Sensitivity
Shape
Sociology
Statistics
Yield Enhancement
Yield Management
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Summary:This paper reports on a new approach to capture the impact of marginal pattern geometries on occurrence of systematic yield-limiting defects. Layout profiling and Hot-Spot checking techniques were used to mark new incoming device layout for regions that approached the known marginal pattern geometries at a varying degree of match quality. Further these regions were translated into inputs for advanced high-sensitivity wafer inspection tools of the Broadband Plasma family with Context Based Inspection capability. Finally specially prepared wafers for this device were exercised through high sensitivity targeted inspections to assess the defect occurrence at each of the regions picked based on layout profiling. Finally all the data was assimilated into an easy-to-interpret visual which shows where the printing margins are smallest on this device.
ISSN:1078-8743
2376-6697
DOI:10.1109/ASMC.2015.7164486