An input pole tuned switching equalization scheme for high-speed serial links

A novel receiver equalization scheme for high-speed links is described in this paper. By per-bit switching the channel-receiver connection, the channel induced inter-symbol interference (ISI) is compensated by receiver (RX) input pole induced ISI. The polarity of the recovered binary bit is adjusted...

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Bibliographic Details
Published in2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
Main Authors Sanquan Song, Jian Xu, Fengxiang Cai, Xin Ma, Zibing Yang, Becker, Matthew, Tate, Larry, Byungsub Kim, Palermo, Samuel, Bowhill, Bill
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2015
Subjects
Attenuation
Clocks
CMOS integrated circuits
equalization
Filtering theory
high-speed links
peaking
residue
Resistors
Switches
switching equalization
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Summary:A novel receiver equalization scheme for high-speed links is described in this paper. By per-bit switching the channel-receiver connection, the channel induced inter-symbol interference (ISI) is compensated by receiver (RX) input pole induced ISI. The polarity of the recovered binary bit is adjusted in digital domain to match the transmitted data. An input pole based two-way interleaved switching equalization circuit is proposed and simulated. In comparison with the conventional FIR filter, it improves the output eye width by 63%. This paper provides a new way of converting a low-pass system into a peaking system for link designs, suitable for a broader range of applications.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2015.7282031