Case Study of Testing a SoC Design with Mixed EDT Channel Sharing and Channel Broadcasting

Modern large SoC designs typically have many cores. Each core requires a certain number of input / output test channels. At the chip level, however, the total number of test channels is limited such that all core-level test channels cannot be accessed at the same time. One solution to this problem i...

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Bibliographic Details
Published in2016 IEEE 25th North Atlantic Test Workshop (NATW) pp. 12 - 17
Main Authors Xiao Liu, Changkai Yu, Yu Qi, Yu Huang, Fu, James
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2016
Subjects
Broadcasting
Channel Broadcasting
Channel sharing
Compression
Discrete Fourier transforms
IP networks
Logic gates
Multicore processing
Pins
SoC test
Testing
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Summary:Modern large SoC designs typically have many cores. Each core requires a certain number of input / output test channels. At the chip level, however, the total number of test channels is limited such that all core-level test channels cannot be accessed at the same time. One solution to this problem is obviously using hierarchical pattern retargeting, where cores can be wrapped and tested individually. Another solution is to use channel sharing / channel broadcasting. The first solution is scalable and good for very large designs. The second solution is good for medium-sized designs that can still run ATPG at the chip level. In this paper, we would like to share our SoC testing experience with one medium-sized case and using channel sharing / broadcasting methodology. Experimental results show that with the proposed SoC test methodology, the total test time can be reduced up to about 2X.
DOI:10.1109/NATW.2016.10