Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip

• Published in: 2015 25th International Conference on Field Programmable Logic and Applications (FPL) pp. 1 - 2
• Main Authors: Fusella, Edoardo, Cilardo, Alessandro, Mazzeo, Antonino
• Format: Conference Proceeding
• Language: English
• Published: Imperial College 01.09.2015
• Subjects: Bridges; Field programmable gate arrays; Integrated circuit interconnections; Parallel processing; Schedules; System-on-chip; Topology
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2015.7293989

Multi-Processor System-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection architectures determining various trade-offs between cost and performance. An automated methodology for optimizing FPGA-based MPSoC interconnect architectures is summarized in this poster paper. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism while containing area and power costs.