A VLSI architecture for the QR decomposition based on the MCGR algorithm

This article presents a VLSI (Very Large Scale of Integration) architecture for the QR decomposition (QRD) based on the Modified Complex Givens Rotations (MCGR) algorithm. Being the QRD a fundamental matrix-computation tool for factorizing matrices (matrix decomposition), its vast set of application...

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Bibliographic Details
Published in2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig) pp. 1 - 6
Main Authors Cervantes-Lozano, Pedro, Gonzalez-Perez, Luis F., Garcia-Garcia, Andres D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2013
Subjects
Arrays
Complexity theory
CORDIC processors
Indexes
Matrix decomposition
MIMO systems
Modified Complex Givens Rotations
Program processors
QR decomposition
systolic arrays
Very large scale integration
VLSI architectures
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Summary:This article presents a VLSI (Very Large Scale of Integration) architecture for the QR decomposition (QRD) based on the Modified Complex Givens Rotations (MCGR) algorithm. Being the QRD a fundamental matrix-computation tool for factorizing matrices (matrix decomposition), its vast set of applications is extended to solve several engineering problems in many areas. For example, in the context of Spatial-Multiplexing Multiple-Input Multiple-Output (SM-MIMO) systems, signal processing tasks oriented to decoding purposes are alleviated by the use of pre-processing modules based on a QRD kernel. Under this topic, several techniques are available for implementing the QRD. The classical techniques used for these purposes are: the Modified Gram-Schmidt Orthogonalization (MGS), the Householder Transformations (Hd-t), and indeed the MCGR. The MCGR algorithm is chosen due to its best trade-off between complexity and numerical precision, as well as offering suitability for VLSI architectures. Synthesis results for this VLSI architecture over FPGA (Field Programmable Gate Array) devices are reported. The flexible and scalable design for the MCGR algorithm incorporates CORDIC (Coordinate Rotation Digital Computer) processors and systolic arrays within its configuration, improving hardware complexity and temporal performance, and evidencing competitive aspects against other related solutions.
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2013.6732267