High throughput LDPC code and decoder design for HINOC 2.0 systems

• Published in: 2015 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting pp. 1 - 5
• Main Authors: Yijin Zhao, Yin Xu, Kang Zhao, Dazhi He, Wenjun Zhang, Hongbin Li, Jingfei Cui
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2015
• Subjects: Channel coding; Decoding; Future technologies and services of broadcasting; High performance network over coax (HINOC); IEEE 802.16 Standard; Iterative decoding; Low density parity check (LDPC) codes; Parallel high throughput LDPC decoder; Random access memory; Throughput
• ISSN: 2155-5044; 2155-5052
• DOI: 10.1109/BMSB.2015.7177211

This paper presents a high-throughput structured low density parity check (LDPC) code and an optimal parallel decoder architecture with advanced Ping-Pong RAMs for the HINOC 2.0 systems. An additional iteration scheme is proposed to further improve decoding performance by taking full use of time intervals of the discontinuous streams, an important feature in HINOC 2.0 systems. The proposed LDPC code proves to be of better performance than the codes adopted in the current standards (802.16e). The proposed decoder is implemented and synthesized on FPGA Stratix V, with the maximum working frequency of 145MHz. The total resource cost is reduced by 23%, which is the cost of one decoder core, with slightly increased complexity in control logics, compared with the traditional Ping-Pong RAM based parallel architecture. The resulting performance is 2Gbps which is enough to support HINOC 2.0 systems.