Co-simulation framework for networked multi-core chips with interleaving discrete event simulation tools

The simulation of networked multi-core chips is a significant research problem in large embedded applications. Although multi-core processors in embedded systems offer increased computational resources and performance, many applications still require distributed systems with multiple of these proces...

Full description

Saved in:
Bibliographic Details
Published in2015 IEEE 20th Conference on Emerging Technologies & Factory Automation (ETFA) pp. 1 - 8
Main Authors Owda, Zaher, Abuteir, Mohammed, Obermaisser, Roman
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2015
Subjects
Computational modeling
Data models
Mathematical model
Object oriented modeling
Synchronization
System-on-chip
Online AccessGet full text

Cover

More Information
Summary:The simulation of networked multi-core chips is a significant research problem in large embedded applications. Although multi-core processors in embedded systems offer increased computational resources and performance, many applications still require distributed systems with multiple of these processors to satisfy resource requirements and provide fault-tolerance at system level. This paper introduces a framework for the co-simulation of a distributed system (i.e., off-chip networks, end-systems) with multi-core chips based on networks-on-a-chip. Simulation components are presented for the synchronization and data exchange between these simulators. A realization is performed using the simulator GEM5 for the chip level, the simulator OPNET for the cluster level and components for communication and synchronization via TCP/IP. An evaluation for a use case demonstrates the utility of the framework to analyse applications and their timing on networked multi-core chips.
ISSN:1946-0740
1946-0759
DOI:10.1109/ETFA.2015.7301418