A 120 nW, Tunable, PVT Invariant Voltage Reference with 80 dB Supply Noise Rejection
This work presents a process, voltage and temperature (PVT) invariant tunable voltage reference generator in 180 nm CMOS technology. Using weighted averaging of tuned PTAT and CTAT voltages at zero temperature coefficient point, the proposed design exhibits only ±0.28% variation in post-layout simul...
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Published in | 2015 IEEE International Symposium on Nanoelectronic and Information Systems pp. 181 - 184 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.12.2015
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Subjects | |
Online Access | Get full text |
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Summary: | This work presents a process, voltage and temperature (PVT) invariant tunable voltage reference generator in 180 nm CMOS technology. Using weighted averaging of tuned PTAT and CTAT voltages at zero temperature coefficient point, the proposed design exhibits only ±0.28% variation in post-layout simulation across process corners over a temperature range of-25 degree C to 100 degree C. Maximum deviation (±3 sigma/mean) from the desired value of the reference voltage is ±2.1% in the untuned case, as obtained from 1000 Monte Carlo runs. Worst case temperature and power supply sensitivity of the tuned reference across process corners are 45 ppm/degree C with 1.8 V supply and 0.18%/V at 27 degree C, respectively. Power supply noise rejection (PSNR) for frequencies between 100 Hz and 100 MHz is > 80dB, with a maximum PSNR of 90dB near 1 kHz. With the use of sub threshold MOSFETs, the DC power consumed by the design is only 300 nW when operated at a nominal supply voltage of 1.8 V. The circuit works even with a supply voltage as low as 0.8 V, while consuming 120 nW DC power. |
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DOI: | 10.1109/iNIS.2015.45 |