Enabling highly energy efficient WSN through PLL-free, fast wakeup radios

• Published in: 2015 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2573 - 2576
• Main Authors: Thirunarayanan, Raghavasimhan, Ruffieux, David, Enz, Christian
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2015
• Subjects: Computer architecture; fast wakeup; FBAR; Film bulk acoustic resonators; Frequency shift keying; Microprocessors; Mixers; PLL-free Radios; Receivers; Tuning; WSN
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2015.7169211

Energy wasted during the wake-up of radios significantly degrades the efficiency of duty-cycled Wireless Sensor Networks (WSN). The major contributor to this energy wastage is the PLL-based frequency synthesizer which has a long wakeup time. Furthermore, the rate of duty cycling in these radios is also constrained by the PLL which imposes an upper limit on the maximum data rate that can be achieved by the radio. In order to improve upon both these bottlenecks, this paper presents an overview of highly agile, PLL-free radios based on FBAR DCOs. These synthesizers have the advantage of a 5μs wakeup, thereby reducing the energy wastage. In addition, they also support high-data rates (upto 16 Mbps) thereby increasing the rate of duty cycling which also improves the energy efficiency. The extremely low phase noise of the FBAR is an added advantage that has been leveraged to provide a low power channel selection filter for a sub-sampling receiver architecture.