Compiling HPC Kernels for the REDEFINE CGRA

• Published in: 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems pp. 405 - 410
• Main Authors: Madhu, Kavitha T., Das, Saptarsi, Nalesh, S., Nandy, S. K., Narayan, Ranjani
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2015
• Subjects: Architecture; Bandwidth; CGRA; Compiler; Computer architecture; Fabrics; HPC; Kernel; Loop; Parallel processing; Pipelines; Synchronization
• DOI: 10.1109/HPCC-CSS-ICESS.2015.139

In this paper, we present a compilation flow for HPC kernels on the REDEFINE coarse-grain reconfigurable architecture (CGRA). REDEFINE is a scalable macro-dataflow machine in which the compute elements (CEs) communicate through messages. REDEFINE offers the ability to exploit high degree of coarse-grain and pipeline parallelism. The CEs in REDEFINE are enhanced with reconfigurable macro data-paths called HyperCells that enable exploitation of fine-grain and pipeline parallelism at the level of basic instructions in static dataflow order. Application kernels that exhibit regularity in computations and memory accesses such as affine loop nests benefit from the architecture of HyperCell [1], [2]. The proposed compilation flow aims at exposing high degree of parallelism in loop nests in HPC application kernels using polyhedral analysis and generates meta-data to effectively utilize the computational resources in HyperCells. Memory is explicitly managed through compiler's assistance. We address the compilation challenges such as partitioning with load balancing, mapping and scheduling computations and management of operand data while targeting multiple HyperCells in the REDEFINE architecture. The proposed solution scales well meeting the performance objectives of HPC computing.