Enabling NoC Performance Improvement Using a Fault Tolerance Mechanism

• Published in: 2015 Brazilian Symposium on Computing Systems Engineering (SBESC) pp. 7 - 12
• Main Authors: Bezerra Lopes, Alba Sandyra, Kreutz, Marcio Eduardo, Magalhaes Pereira, Monica
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2015
• Subjects: Circuit faults; fault tolerance; Fault tolerant systems; Hardware; hardware redundancy; Multiplexing; network on chip; parallelism; Redundancy; spare; Transistors
• ISSN: 2324-7894
• DOI: 10.1109/SBESC.2015.9

In multicore era, enabled by the decrease of transistors size, networks on chips (NoCs) emerged as a fast and scalable solution in replacement to buses systems. While providing high performance, the process of transistors miniaturization affects the dependability of the systems due to increase of fault rates caused by the susceptibility of transistors, wire and connections at deep submicron scale. Despite having replicated routers, NoCs are not designed to support fault tolerance since all routers are used to compose the paths of messages. However, it is possible to connect spare routers on the network topology to replace a faulty one. This ensures system functionality even in the presence of faults. Despite this, while the original router is fault-free, the extra resources are not used and they remain consuming area and power without being properly used. In this paper, we propose a Network-on-Chip comprised by spare routers and combined with a mechanism to explore the gains in performance that could be achieved by using them as regular routers when the system runs without failures. Results confirm the expected performance improvements, validating the proposed solution.