SMV methodology enhancements for high speed I/O links of SoCs

This paper presents an enhanced methodology to validate High Speed I/O links. The methodology outlines a stress method selection process, statistical techniques to optimize volume data collection as well as a method to determine when to perform UPM calculations.

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Bibliographic Details
Published in2014 IEEE 32nd VLSI Test Symposium (VTS) pp. 1 - 5
Main Authors Viveros-Wacher, Andres, Alejos, Ricardo, Alvarez, Liliana, Diaz-Castro, Israel, Marcial, Brenda, Motola-Acuna, Gaston, Vega-Ochoa, Edgar-Andrei
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2014
Subjects
Hidden Markov models
High Speed I/O
Monte Carlo methods
Post-Silicon Electrical Validation
Sociology
Stress
System Marginality Validation
System-on-chip
Unit per Million
Voltage measurement
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Summary:This paper presents an enhanced methodology to validate High Speed I/O links. The methodology outlines a stress method selection process, statistical techniques to optimize volume data collection as well as a method to determine when to perform UPM calculations.
ISSN:1093-0167
2375-1053
DOI:10.1109/VTS.2014.6818767