Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier

This paper presents an area-efficient low-power architecture for configurable booth multiplier. It is synthesized and post-layout simulated using 90 nm CMOS process and it occupies 9511 μm 2 and consumes 1.73 mW at 167 MHz. Comparatively, the proposed multiplier architecture requires 43.12% and 75.6...

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Bibliographic Details
Published in2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) pp. 599 - 600
Main Authors Shrestha, Rahul, Rastogi, Utkarsh
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.01.2016
Subjects
Architecture
Booth multiplier
Clocks
CMOS
Conferences
Configurable
Consumption
Design engineering
digital architectures
finite state machine
Generators
Logic gates
Multiplexing
Multipliers
Silicon
Simulation
Switches
Very large scale integration
VLSI
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Summary:This paper presents an area-efficient low-power architecture for configurable booth multiplier. It is synthesized and post-layout simulated using 90 nm CMOS process and it occupies 9511 μm 2 and consumes 1.73 mW at 167 MHz. Comparatively, the proposed multiplier architecture requires 43.12% and 75.65% lower area and power, respectively, in comparison with the state of the art work.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
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SourceType-Conference Papers & Proceedings-2
ISSN:2380-6923
DOI:10.1109/VLSID.2016.36