Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors

• Published in: 2015 IEEE International Integrated Reliability Workshop (IIRW) pp. 63 - 67
• Main Authors: Jen-Hao Lee, Chen, Eliot S. H., Yung-Huei Lee, Chun-Hung Lin, Chun-Yu Wu, Ming-Han Hsieh, Huang, Kevin, Jhong-Sheng Wang, Yung-Sheng Tsai, Lu, Ryan, Jiaw-Ren Shih
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.10.2015
• Subjects: BTI; Computer simulation; CPI; Degradation; FEM; FinFET; FinFETs; Finite element analysis; HCI; HK/MG; Logic; mobility; Modelling; Nanostructure; Performance evaluation; Semiconductor devices; Strain; Stress; Stresses; Transistors
• ISBN: 1467373958; 9781467373951
• ISSN: 2374-8036
• DOI: 10.1109/IIRW.2015.7437068

Despite chip-package interaction (CPI) has been extensively used in nano-electronics industry, impact of CPI stress on transistor performance and reliability remains unclear. In this work, performance change of transistor featuring HK/MG planar and FinFET by 4-point bending experiments were conducted to study stress evolution. Finite-element modeling (FEM) simulation revealed that P-FinFET mobility change is less sensitive to applied stress than planar. Device reliability as BTI/HCI and ring oscillator frequency drift of both planar and FinFET are all immune to strain. Moreover, FinFET mobility degradation caused by NBTI is independent of strain type, due to its fully-depleted regime. Management of carrier mobility shifts and transistor aging by optimized chip package technology are also presented in this study.