A simple divide-and-conquer approach for neural-class branch prediction

• Published in: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) pp. 243 - 254
• Main Author: Loh, G.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Accuracy; Adders; Counting circuits; Delay; Frequency; Hardware; History; Machine learning algorithms; Piecewise linear techniques; Pipeline processing
• ISBN: 076952429X; 9780769524290
• ISSN: 1089-795X; 2641-7944
• DOI: 10.1109/PACT.2005.6

The continual demand for greater performance and growing concerns about the power consumption in high-performance microprocessors make the branch predictor a critical component of modern microarchitectures. Recent research in applying machine learning techniques to the branch prediction problem has shown incredible improvements in branch prediction accuracy by exploiting correlations in very long branch histories. Nevertheless, these techniques have not been adopted by industry due to the high implementation complexity. In this paper, we propose a global-history divide-and-conquer (gDAC) branch predictor that achieves IPC rates that are near that of the best neural predictors, but remains easy to implement because they only make use of simple tables of saturating counters. We show how to use ahead-pipelining to implement our gDAC predictor with a single-cycle effective latency. Our gDAC predictor achieves higher performance (IPC) than the original global history perceptron predictor across all predictor sizes evaluated, and outperforms the path-based neural predictor for predictors 16KB and larger. At 128KB, gDAC even achieves an IPC rate equal to the recently proposed piecewise-linear neural branch predictor.