Negative bias temperature instability in triple gate transistors

• Published in: 2004 IEEE International Reliability Physics Symposium. Proceedings pp. 8 - 12
• Main Authors: MAEDA, Shigenobu, CHOI, Jung-A, YANG, Jeong-Hwan, JIN, You-Seung, BAE, Su-Kon, KIM, Young-Wug, SUH, Kwang-Pyuk
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Annealing; Applied sciences; Degradation; Electronics; Etching; Exact sciences and technology; MOSFETs; Negative bias temperature instability; Niobium compounds; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Stress; Titanium compounds; Transistors; Thermal stress; Voltage threshold; Density of states; Electric stress; Transistor gate; Planar transistor; Damaging
• ISBN: 9780780383159; 078038315X
• DOI: 10.1109/RELPHY.2004.1315293

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The -direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.