A high-speed power and resolution adaptive flash analog-to-digital converter

• Published in: IEEE International SOC Conference, 2004. Proceedings pp. 33 - 36
• Main Authors: Nahata, S., Kyusun Choi, Jincheol Yoo
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Analog-digital conversion; Applied sciences; Binary codes; Circuit properties; CMOS technology; Computer science; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Integrated circuits; Inverters; Power engineering and energy; Read only memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Signal resolution; Threshold voltage; Power consumption; AD converter; Complementary MOS technology; Coding circuit; Integrated circuit; System on a chip; Comparator circuit; DA converter; Electrical standby; Switching
• ISBN: 9780780384453; 0780384458
• DOI: 10.1109/SOCC.2004.1362342

A high-speed and small-area power and resolution adaptive flash ADC is presented. The high-speed power and resolution adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 /spl mu/m and 0.07 /spl mu/m CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.