Silicon nanocrystals: from Coulomb blockade to memory arrays

• Published in: 4th IEEE Conference on Nanotechnology, 2004 pp. 290 - 292
• Main Authors: Steimle, R.F., Rao, R., Sadd, M., Swift, C., Hradsky, B., Straub, S., Merchant, T., Stoker, M., Parikh, C., Anderson, S., Rossow, M., Yater, J., Acred, B., Harber, K., Prinz, E., White, B.E., Muralidhar, R.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Applied sciences; Capacitance; CMOS technology; Design. Technologies. Operation analysis. Testing; Electronics; Electrons; Energy states; Exact sciences and technology; Fabrication; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Molecular electronics, nanoelectronics; Nanocrystals; Nonvolatile memory; Pressure control; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Storage and reproduction of information; Threshold voltage; Memory devices; Confinement; Nucleation; Power supply; Erasure; Nanoelectronics; Flash memory; Non volatile memory; Complementary MOS technology; Integrated circuit; Recording; Coulomb blockade; Nanocrystal; Passivation
• ISBN: 0780385365; 9780780385368
• DOI: 10.1109/NANO.2004.1392328

Silicon nanocrystals provide opportunity to solve the challenging problem of tunnel oxide scaling of conventional flash memories by increasing immunity to charge loss via tunnel oxide defects. New aspects in silicon nanocrystal memory technology include Coulomb blockade or charge confinement effects, atomistic nucleation, and nanocrystal passivation to preserve them during subsequent processing and program/erase endurance characteristics. This paper discusses the above characteristics and culminates in presenting salient results from 4 Mb NOR memory arrays fabricated using 90 nm CMOS technology. Excellent memory characteristics including tight Vt distributions are obtained using a tunnel oxide thickness of 5 nm and a 6 V power supply.