Reliability properties of low voltage PZT ferroelectric capacitors and arrays

• Published in: 2004 IEEE International Reliability Physics Symposium. Proceedings pp. 200 - 208
• Main Authors: Rodriguez, J., Remack, K., Boku, K., Udayakumar, K.R., Aggarwal, S., Summerfelt, S., Moise, T., McAdams, H., McPherson, J., Bailey, R., Depner, M., Fox, G.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Applied sciences; Capacitors; Circuit properties; CMOS logic circuits; CMOS process; Dielectric, amorphous and glass solid devices; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Ferroelectric materials; Integrated circuits; Integrated circuits by function (including memories and processors); Logic arrays; Logic testing; Low voltage; Magnetic and optical mass memories; MOCVD; Packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Storage and reproduction of information; Transistors; Autonomous system; Memory devices; High density; Polycrystal; MOCVD; Information loss; Thin film; Low voltage; Microelectronic fabrication; CMOS logic circuits; Ferroelectric capacitors; Reliability; Activation energy; Ferroelectric storage; Damaging
• ISBN: 9780780383159; 078038315X
• DOI: 10.1109/RELPHY.2004.1315324

We report on the reliability properties of a high-density ferroelectric memory based on a 70nm thick MOCVD PZT process technology. We observe that the polycrystalline texture plays an important role in the electrical and reliability properties of these thin films. Data retention loss is primarily due to the imprint effect, which shows a 1.5eV "Time-to-Fail" activation energy. Good correlation is observed between stand alone test capacitors and memory arrays integrated into a 130nm, 5LM, Cu/FSG logic CMOS process. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ read/write cycles.