Qualification method for DRAM retention by leakage current evaluation using subthreshold characteristics of cell transistors

• Published in: 2004 IEEE International Reliability Physics Symposium. Proceedings pp. 445 - 448
• Main Authors: Young Pil Kim, Beom Jun Jin, Sun-Ghil Lee, Siyoung Choi, Uin Chung, Joo Tae Moon, Kim, S.U.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Applied sciences; Current measurement; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Feedback; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage current; Moon; MOSFETs; Qualifications; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Statistical distributions; Testing; Transistors; Statistical distribution; s parameter; Random access memory; Integrated circuit; Retention factor; Feedback regulation; Transistor; Leakage current; Dynamic random access memory
• ISBN: 9780780383159; 078038315X
• DOI: 10.1109/RELPHY.2004.1315369

We suggested a new qualification method for DRAM retention property by evaluation of a cell transistor leakage current using the subthreshold characteristic parameters, V/sub th//S and dV/sub th//dV/sub BS/. Correlation between the Leakage current Evaluation Parameter (LEP) which is obtained from the method and the retention time of the DRAM products was carried out. The result shows that the measurement limitation imposed by the extremely small cell transistor leakage current can be overcome by the new method, and provides quick feedbacks on the retention characteristics at the early stage of process integration and qualification cycles. During the correlation procedure, we also investigated on the statistical distribution of the retention time of the DRAM cells.