DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

• Published in: 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings pp. 166 - 173
• Main Authors: Bingfeng Mei, Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY IEEE 2002
• Subjects: Applied sciences; Computer architecture; Computers, microcomputers; Concrete; Electronics; Exact sciences and technology; Field programmable gate arrays; Hardware; Input-output equipment; Kernel; Parallel processing; Reconfigurable architectures; Scheduling algorithm; Testing; Topology; VLIW; Performance evaluation; Compiler; Circuit design; Parallelism; Scheduling; Reconfigurable architectures; Algorithm; Computer aided design; Data flow

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are ad...