DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are ad...

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Bibliographic Details
Published in2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings pp. 166 - 173
Main Authors Bingfeng Mei, Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.
Format Conference Proceeding
LanguageEnglish
Published New York, NY IEEE 2002
Subjects
Applied sciences
Computer architecture
Computers, microcomputers
Concrete
Electronics
Exact sciences and technology
Field programmable gate arrays
Hardware
Input-output equipment
Kernel
Parallel processing
Reconfigurable architectures
Scheduling algorithm
Testing
Topology
VLIW
Performance evaluation
Compiler
Circuit design
Parallelism
Scheduling
Reconfigurable architectures
Algorithm
Computer aided design
Data flow
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Summary:Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstraction generates an internal graph representation from a concrete architecture description. A modulo scheduling algorithm is key to exploit parallelism and achieve high performance. The experimental results show up to 28.7 instructions per cycle (IPC) over tested kernels.
ISBN:0780375742
9780780375741
DOI:10.1109/FPT.2002.1188678