An Implementation of a Pattern Matching Accelerator on a RISC-V Processor

This paper proposes a pattern matching accelerator and implements it on a RISC-V processor. The proposed pattern matching accelerator counts the number of times input data matches multiple registered data. The accelerator could be used by custom instructions added to a RISC-V processor, and the patt...

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Bibliographic Details
Published in2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW) pp. 273 - 275
Main Authors Takayama, Riku, Tada, Jubee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2022
Subjects
Benchmark testing
Codes
Conferences
Field programmable gate arrays
Generators
Impedance matching
Logic gates
Microprocessors
Pattern matching
RISC-V
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Summary:This paper proposes a pattern matching accelerator and implements it on a RISC-V processor. The proposed pattern matching accelerator counts the number of times input data matches multiple registered data. The accelerator could be used by custom instructions added to a RISC-V processor, and the pattern matching process can be accelerated by using these instructions. As a benchmark, a program that counts the number of times the grid square codes converted from randomly generated latitudes and longitudes match the registered grid square codes is used. Experimental results show the RISC-V processor with the proposed accelerator achieves 52.7% reduction of execution time compared to the original processor.
ISSN:2832-1324
DOI:10.1109/CANDARW57323.2022.00059