Electrical Performance Enhancement Solution with FO-EB in HPC Application

• Published in: 2023 24th International Conference on Electronic Packaging Technology (ICEPT) pp. 1 - 5
• Main Authors: Su, Po Yuan James, Ho, David, Wang, Yu Po, Pu, Jacy, Shih, Teny, Lin, Sam
• Format: Conference Proceeding
• Language: English
• Published: IEEE 08.08.2023
• Subjects: Bridge circuits; Bridges; Capacitors; Fan-out Embedded Bridge (FO-EB); High performance computing; High Performance Computing (HPC); Integrated Passive Device (IPD); Noise; Performance evaluation; System on Chip (SoC); Voltage
• ISSN: 2836-9823
• DOI: 10.1109/ICEPT59018.2023.10492332

Since the Video Media has changed the way to provide the service, the cloud service become the most popular mode to provide video streaming and the high performance computing (HPC) become the most important for this kind of service. It is not only the high band width has been required, but also the high electrical performance. In terms of providing the better electrical performance for HPC, we need to consider about the packaging design. There are several ways can enhance electrical performance, and the first one would be the System on Chip (SoC) size increasing which contains more transistors providing better electrical performance, and it is the simple design solution for a SoC chip size with a package size increasing. Refer to Figure 1. Chip Size Increasing with Better Performance.Today, the package of high speed design has included the capacitor to prevent the AC noise, and the signal protection and stable the voltage is the must request for the package design. By using the Integrated Passive Device (IPD) capacitor can reduce the AC noise, and it is the best design way to enhance the AC noise for the better electrical performance. The major purpose to use FO-EB package is cost saving because the advanced node with low yield of larger silicon chip size is really expensive. So using the chiplet to connect with embedded bridge die, and the bridge die can do the communications with high electrical performance. Accompany by bridge die and HBM Integration, the FO-EB package of the high bandwidth memory also has good electrical performance as well as 2.5D package. The FO-EB package has integrated silicon bridge die which means to use the silicon bridge die to connect with spilt dies. It is not only can provide the short distance, but also become more flexable for the package design. The FO-EB can contribute the good electrical performance in HPC application and this package can also provide the good warpgae.In this paper, we like to discover the FO-EB design and evaluate the FO-EB perofrmance including the package warpage of shadow Moire, the HBM electrical preformance and also do the IPD design for the AC noisy. And, the chiplets Integration of FO-EB Package solution would be the best choice in HPC Application. Refer to Figure 2. High Performance Computing.