Run, Don't Walk: Chasing Higher FLOPS for Faster Neural Networks

• Published in: Proceedings (IEEE Computer Society Conference on Computer Vision and Pattern Recognition. Online) pp. 12021 - 12031
• Main Authors: Chen, Jierun, Kao, Shiu-hong, He, Hao, Zhuo, Weipeng, Wen, Song, Lee, Chul-Ho, Chan, S.-H. Gary
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2023
• Subjects: Convolution; Deep learning architectures and techniques; Feature extraction; Focusing; Graphics processing units; Industries; Memory management; Neural networks
• ISSN: 1063-6919
• DOI: 10.1109/CVPR52729.2023.01157

To design fast neural networks, many works have been focusing on reducing the number of floating-point operations (FLOPs). We observe that such reduction in FLOPs, however, does not necessarily lead to a similar level of re-duction in latency. This mainly stems from inefficiently low floating-point operations per second (FLOPS). To achieve faster networks, we revisit popular operators and demonstrate that such low FLOPS is mainly due to frequent memory access of the operators, especially the depthwise con-volution. We hence propose a novel partial convolution (PConv) that extracts spatial features more efficiently, by cutting down redundant computation and memory access simultaneously. Building upon our PConv, we further propose FasterNet, a new family of neural networks, which attains substantially higher running speed than others on a wide range of devices, without compromising on accuracy for various vision tasks. For example, on ImageNet-lk, our tiny FasterNet-TO is 2.8×, 3.3×, and 2.4× faster than MobileViT-XXS on GPU, CPU, and ARM processors, respectively, while being 2.9% more accurate. Our large FasterNet-L achieves impressive 83.5% top-1 accuracy, on par with the emerging Swin-B, while having 36% higher inference throughput on GPU, as well as saving 37% compute time on CPU. Code is available at https://github.com/JierunChen/FasterNet.