A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement

This paper presents a 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process. The first stage is an asynchronous SAR ADC resolving 6 bits, and the second stage is a time-domain ADC composed of a VTC and a 7-bit SAR TDC (with 1-bit redundancy). To speed up the time domain operation,...

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Bibliographic Details
Published in2023 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Zhao, Yutong, Xiang, Yuguo, Ye, Fan, Ren, Junyan
Format Conference Proceeding
LanguageEnglish
Published IEEE 21.05.2023
Subjects
hybrid ADC
LMS-based calibration
non-binary SAR TDC
ping-pong
voltage-time domain quantization
VTC
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Summary:This paper presents a 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process. The first stage is an asynchronous SAR ADC resolving 6 bits, and the second stage is a time-domain ADC composed of a VTC and a 7-bit SAR TDC (with 1-bit redundancy). To speed up the time domain operation, a ping-pong switching technique is used in the second stage. Besides, a common mode VTC is adopted to improve the linearity during the voltage-to-time conversion. A non-binary SAR TDC is also designed to tolerate the MSBs decision errors in the time-domain quantization. Furthermore, a LMS-based background calibration is performed to correct the capacitor mismatch error, interstage gain error, and bit-weight in the SAR TDC. The simulation results show that this design achieves a SNDR of 63.3 dB and a SFDR of 79.1 dB at Nyquist input. The power consumption is 9.6 mW with a supply of 0.9V, showing a FoM of 20.1 fJ/conversion-step.
ISSN:2158-1525
DOI:10.1109/ISCAS46773.2023.10181657