A 91.9-113.2 GHz Compact Frequency Tripler with 44.6 dBc Peak Fundamental Harmonic-Rejection-Ratio Using Embedded Notch-filters and Area-Efficient Matching Network in 65 nm CMOS

• Published in: 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) pp. 165 - 168
• Main Authors: Huang, Xiangrong, Jia, Haikun, Deng, Wei, Wang, Zhihua, Chi, Baoyong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11.06.2023
• Subjects: CMOS process; frequency tripler; Gain measurement; Harmonic analysis; harmonic rejection ratio; Impedance matching; notch filter; Power distribution; Power measurement; Semiconductor device measurement; transformer; Transformers
• ISSN: 2375-0995
• DOI: 10.1109/RFIC54547.2023.10186124

This article presents a W-band mixer-based frequency tripler. The folded four-coil transformer is proposed to achieve the input matching and input power distribution to the push-push frequency doubler and the mixer simultaneously. The mixer mixes the second-harmonic current with the input fundamental harmonic to obtain the third harmonic. A single-stage class-AB amplifier follows to drive the output load. The fundamental harmonic notch-filters composed of parallel inductor and capacitance tanks are embedded into the interstage and output matching networks to save the chip area and improve the harmonic-rejection-ratio (HRR). The proposed frequency tripler has been fabricated in 65nm CMOS process with a 160 µm × 420 µm core chip area. Measurement results show a conversion gain of −2.35 dB, a 44.6 dBc peak fundamental HRR and a 3.88% DC-RF efficiency for an input power of 6 dBm at 102 GHz. The measured output 3 dB bandwidth is 91.9-113.2 GHz.