FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites

• Published in: 2023 IEEE 98th Vehicular Technology Conference (VTC2023-Fall) pp. 1 - 7
• Main Authors: Palisetty, Rakesh, Eappen, Geoffrey, Singh, Vibhum, Socarras, Luis Manuel Garces, Ha, Vu Nguyen, Vasquez-Peralvo, Juan A., Rios, Jorge Luis Gonzalez, Duncan, Juan Carlos Merlano, Martins, Wallace Alves, Chatzinotas, Symeon, Ottersten, Bjorn, Coskun, Adem, King, Stephen, D'Addio, Salvatore, Angeletti, Piero
• Format: Conference Proceeding
• Language: English
• Published: IEEE 10.10.2023
• Subjects: Array signal processing; Beamforming; Discrete Fourier transforms; fast Fourier transform; look-up table; Power demand; power estimation; quantization; Satellites; Timing; Two dimensional displays; Vehicular and wireless technologies
• ISSN: 2577-2465
• DOI: 10.1109/VTC2023-Fall60731.2023.10333351

On-board processing of digital beamforming in satellites is an efficient solution for the higher data rates, more capacity, and lower latency, but the available on-board limited power makes it impractical to digitally create thousands of beams at once. A significant portion of the analog hardware in a satellite communications payload can be replaced with highly integrated digital components, which are often more affordable, lighter, smaller, and reprogrammable by employing digital beamforming. In comparison to matrix-by-vector multiplication beamforming, the discrete Fourier transform (DFT) beamformer enables the finer realization of real-time beamformers with reduced circuit complexity and lower power consumption. Fast Fourier transform (FFT) methods can further reduce the computing cost of the DFT computation. Therefore, in this paper, area-power efficient two-dimensional (2D) FFT digital beamforming techniques are analyzed and implemented. The major implementation challenge is to produce N samples per cycle with lower area-power consumption. Fully unrolled 4-bit twiddle factor (TF) quantized FFT is proposed in this regard. The optimization techniques through quantization, truncation, and complex multipliers are thoroughly discussed for efficient implementation. The behavioral and post-route timing simulations are validated, and implementation results like area and power consumption are estimated and compared among conventional , fully unrolled, and the proposed 4-bit TF quantized 2D-FFT.