Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications

Artificial intelligence (AI), and particularly large language models, are rapidly advancing capabilities within a range of fields, from personal assistants to medical diagnosis to weather forecasting. This growth is supported by high-performance compute (HPC) datacenters, whose performance has been...

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Bibliographic Details
Published in2024 IEEE Custom Integrated Circuits Conference (CICC) pp. 1 - 7
Main Authors Turner, Walker J., Poulton, John W., Nishi, Yoshinori, Chen, Xi, Zimmer, Brian, Song, Sanquan, Wilson, John M., Dally, William J., Gray, C. Thomas
Format Conference Proceeding
LanguageEnglish
Published IEEE 21.04.2024
Subjects
Bandwidth
Insertion loss
Routing
System integration
Urban areas
Weather forecasting
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Summary:Artificial intelligence (AI), and particularly large language models, are rapidly advancing capabilities within a range of fields, from personal assistants to medical diagnosis to weather forecasting. This growth is supported by high-performance compute (HPC) datacenters, whose performance has been doubling every 2.5 years [1] and is likely to accelerate over time based on demands of future AI applications. These server-class systems consume energy equivalent to a medium-sized city, where significant power is used for data movement between the various modules, boards, racks, and clients throughout the datacenter. The rapidly growing needs of AI-driven compute require increasing communication bandwidth with the highest degree of energy efficiency across all levels of system integration.
ISSN:2152-3630
DOI:10.1109/CICC60959.2024.10529010