Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET

SRAM SER measurements show a decrease in per-bit susceptibility at the 3-nm FinFET node compared to the 5-nm FinFET node, contrary to the trend observed between the 7-nm and 5-nm FinFET nodes. Robust data across various supply voltages demonstrate a pronounced exponential bias influence on 3-nm FinF...

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Bibliographic Details
Published in2024 IEEE International Reliability Physics Symposium (IRPS) pp. 10C.2-1 - 10C.2-4
Main Authors Narasimham, B., Montoya, A. R., Paone, C., Riehle, T., Smith, M., Tsau, L., Ball, D., Bhuva, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 14.04.2024
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Summary:SRAM SER measurements show a decrease in per-bit susceptibility at the 3-nm FinFET node compared to the 5-nm FinFET node, contrary to the trend observed between the 7-nm and 5-nm FinFET nodes. Robust data across various supply voltages demonstrate a pronounced exponential bias influence on 3-nm FinFET SRAM SER, distinguishing it from earlier FinFET processes. Simulation and modeling attribute these trends to variations in Q_{crit} and Q_{coll} . These findings highlight that SER scaling trends in advanced FinFET processes do not necessarily align with the standard scaling trends observed in prior nodes.
ISSN:1938-1891
DOI:10.1109/IRPS48228.2024.10529467