Materials to System Co-optimization (MSCO™) for SRAM and its application towards Gate-All-Around Technology

In this paper, we deploy our SRAM MSCO framework to evaluate the GAA SRAM performance and explore different performance optimization strategies. Our modeling indicates that GAA SRAM can have better stability, writability and read-current compared to FinFET SRAM, primarily due to better electrostatic...

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Published in2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) pp. 53 - 56
Main Authors Vyas, Pratik B., Pal, Ashish, Costrini, Gregory, Asenov, Plamen, Mhedhbi, Sarra, Zhao, Charisse, Moroz, Victor, Colombeau, Benjamin, Haran, Bala, Bazizi, El Mehdi, Ayyagari-Sangamalli, Buvna
Format Conference Proceeding
LanguageEnglish
Published The Japan Society of Applied Physics 27.09.2023
Subjects
circuit design
device modeling
DTCO
FinFET
FinFETs
GAA
Gallium arsenide
Logic gates
Performance evaluation
Random access memory
Semiconductor process modeling
SNM
SRAM
Stability analysis
Write Margin
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Summary:In this paper, we deploy our SRAM MSCO framework to evaluate the GAA SRAM performance and explore different performance optimization strategies. Our modeling indicates that GAA SRAM can have better stability, writability and read-current compared to FinFET SRAM, primarily due to better electrostatics and drive-strength ratio between nMOS and pMOS. Furthermore, we show that design optimizations through varying nanosheet count, nanosheet width and RMG workfunction allows GAA SRAM to be tailored for different applications.
DOI:10.23919/SISPAD57422.2023.10319497